The present invention relates to chip carriers.
In conventional leadless chip-carriers, multiple layers of ceramic (usually alumina-based) are fired together to produce a structure having a cavity in which an integrated circuit chip can be mounted. The chip is connected to bond pads on a shelf inside the cavity, and a lid (e.g. of molybdenum, ceramic, or Kovar) is soldered on to make a hermetic seal on the cavity. Some of the ceramic layers which make up the chip carrier have metal traces patterned on them before firing, to make connections between the bond pads inside the hermetically sealed cavity and contacts on the outside of the chip carrier. Thus, the chip carrier can be mounted on a circuit board by making contact to its external contacts, while the chip remains hermetically isolated.
This technology is fairly mature and reliable, but some of its limitations must now be overcome. For example, at present there is a tremendous thrust towards finding ways to include multiple chips in a chip carrier. While it is possible to put more than one chip in the chip cavity and bond them out using conventional technology, this straightforward approach runs into several problems. One problem is footprint; putting four chips into a carrier should ideally require much less board area than four separate one-chip carriers would; but this advantage will not be fully obtained with prior art technology. Another problem is interconnect; the interconnect topologies permitted by the prior art chip carriers tend to be fairly simple, but optimal design of multi-chip modules would be greatly facilitated by more complex interconnect, particularly if the interconnect routing were reconfigurable, i.e. could be changed for a given cofired-ceramic structure without having to design a new cofired-ceramic structure.
One way to achieve higher density per unit board area in multi-chip chip carriers would be to find some way to stack more than one layer of chips inside the carrier, but some way to make thermal and electrical connection to the upper layer of chips is necessary. Chips generate heat during operation, and in conventional technology much of this heat flows from the chips through the chip carrier's bottom surface (on which the chips are mounted) down through the circuit board; but this thermal path will not be available for all chips if more than one layer of chips is used. Thus, the problem of thermal dissipation is a major barrier to multi-chip packaging.
The present invention permits higher density in multichip carriers, by providing a chip carrier with improved packing density, wherein at least one layer of chips is bonded not to the substrate, but rather to the lid. The present invention replaces the metal lid conventionally used for hermetic sealing with a ceramic lid which includes multiple through vias. A chip can be mounted on the inside of the lid and bonded to pads which are connected, through the vias, to the exterior of the lid. The contacts on the outside of the lid can then be used in a variety of ways. For example, a TAB strip (i.e. a strip of a flexible polymer with conductive traces patterned on it, as used in tape-automated bonding) can be used to connect these contacts to other contacts near the edge of the upper surface of the package; some of these upper surface contacts may be connected, through castellated vias which lead all the way up the side of the package, to external contact pads at the bottom edge of the chip carrier, which can be used to make electrical contact to the circuit board; others of these upper surface contacts may be connected, through traces inside the chip carrier body, to contact pads which make contact with the lower layer of chips, to provide a local bus. Since the connection from the via tops to the upper surface contacts is made after the package is hermetically sealed, the electrical configuration of the package is now reconfigurable. That is, one co-fired ceramic body may be used for a wide variety of interconnect configurations, since the interconnect configuration may be changed by altering the bonding used on the top of the chip carrier.
Moreover, the vias through the lid which the present invention provides may also be used to provide the thermal contact to the chips mounted on the lid. That is, some through vias may not be used for electrical interconnect, but merely for thermal interconnect; and various means known in the prior art may be used to dissipate heat from the outside of the lid. Thus, the present invention provides a multi-chip chip carrier where chips can be mounted in more than one layer, and the upper layer of chips has good heat-sinking.
The present invention also provides a multi-chip chip carrier with a very compact footprint.
The present invention also provides a new routing for interconnect between the chips and the external contact pads of a chip carrier, which permits interconnect topologies which would not otherwise be possible.
Another recent pressure on chip-carrier interconnect technology arises from the increasing use of processors having huge pinout numbers. For example, some kinds of symbolic processors or signal processors may have chip pinouts much greater than 100. This puts tremendous pressure on the interconnect capabilities of the conventional package. Often the interconnect demands on the package external pinouts and on the board can be reduced if such a processor can be packaged together with one or more support chips (such as, e.g., cache memory, bus manager, coprocessor, etc.) to form (in effect) a local bus inside a single package. However, conventional chip carrier technology does not have the interconnect routing flexibility to make such local bus configurations readily achievable.
The present invention may be particularly advantageous in embodiments which use a pad grid type chip carrier, since the contacts along the edge of the chip carrier can be used for bonding out the interconnects which derive from the lid of the carrier, and the other interconnects can be brought out to pads which are not at the edge of the carrier's underside.
Another application of the topside interconnect may be to provide a local bus between carriers; that is, a short TAB strip could be used to connect the topside contacts of one carrier to the topside contacts of one or more adjacent carriers. This configuration is not preferred, since it makes rework, inspection, and testing more difficult, but it does give the board designer another option for interconnect, which may occasionally be advantageous.
Another advantage of the present invention is reliability; organic materials inside a package are a potential source of contaminants, and the present invention provides a way in which the use of organic materials inside the hermietically sealed cavity can be reduced (or avoided altogether), while still taking advantage of the gang bonding and other advantages of TAB technology. That is, the chips mounted on the inside of the lid can be connected to the vias by short bond wires, and TAB strips can be used to make the connections to the via top ends on the outside of the package.
It should be noted that the elements which are to be mounted on the inner surface of the lid do not have to be integrated circuits; some or all of them may be passive components. In fact, the present invention provides a particularly advantageous technology for packaging passive components together with integrated circuits; if a set of passive components is provided in the lid, with their leads brought out through the vias in the lid, discretionary wiring may be used (after the package is sealed) to selectively connect the chips in the package to various ones of the discrete passive elements. Thus, for example, an rf circuit may be reconfigured, by late discretionary interconnects, to operate at any one of several frequencies. Another way of considering this advantage of the invention is that the present invention permits chip carriers to take over some functions which were previously the province of hybrid modules only.
One of the interconnect routings suggested in the prior art of chip carriers is to run vias through the bottom of the chip carrier, so that down-bonding of the chip onto via tops on the floor of the carrier can be connected to (for example) pad grid contacts on the bottom exterior of the carrier. It has been found that, where it is desired to run a via essentially straight through a ceramic wall, hermeticity is best assured by making the via crooked. That is, the via is not simply run straight through, but the layer which is to include the via is constructed as two layers to be fired together; the two layers have matching but slightly offset sets of vias, with a very short lateral trace to join them. This prevents migration of moisture and other contaminants along the microcracks which often form parallel to the via. For similar reasons, the vias through the package lid used in the present invention are preferably formed crooked, to help provide hermeticity.
In addition, the lateral traces used inside the lid do not strictly have be short, nor need they be used merely to join slightly misaligned vias in the layers which make up the lid. In alternative embodiments, these lateral traces buried within the lid may be used to provide still further interconnect complexity. The price of this will normally be that the vias in the lid cannot be made as dense as would otherwise be possible, but in many applications the additional options in interconnect topology may well be worth it.
According to the present invention there is provided: A chip carrier comprising; a chip carrier body defining a cavity therein, said cavity having a substantially planar mounting surface at the bottom thereof and one or more bonding ledges in proximity to said mounting surface within said cavity; external contacts on the exterior of said chip carrier body; a lid hermetically sealed to enclose said cavity in said chip carrier body, said lid comprising conductive vias therethrough; and one or more integrated circuit chips enclosed between said lid and said body within said cavity.